I am currently a Postdoctoral Fellow at the Hong Kong University of Science and Technology and a staff of the AI Chip Center for Emerging Smart Systems (ACCESS) under InnoHK. I received the B.S. degree in Mechano-Electronic Engineering from Xidian University in 2017, and the Ph.D. degree in Electronic Science and Technology from the University of Science and Technology of China in 2023 under the supervision of Prof. Yi Kang. My research interests include efficient neural network algorithms and their implementation on chips. I have published more than 16+ papers at top international conferences (DAC, CICC, ASP-DAC, ISCAS) and journals (AFM, TCAS-II, TVLSI, TODES, CHIP), with total Google Scholar citations 290+ (You can also use the Google Scholar badge ). You can find more information through my CV. Welcome to contact me if you have any interests in collaboration.

E-mail: zihaoxuan@ust.hk | WeChat: ZihaoXUAN-numX

📖 Educations

2017.09 - 2023.06, PhD in Electronic Science and Technology, School of Microelectronics, University of Science and Technology of China.
2013.09 - 2017.06, Bachelor in Electronic Packaging Technology, School of Mechano-Electronic Engineering, Xidian University. GPA: 3.86/4.00, Rank:1/33

💻 Work Experience

2023.10 - Present, Postdoctoral Fellow in AI Chip Center for Emerging Smart System, The Hong Kong University of Science and Technology.

🎖 Honors and Awards

2023-Present, Hong Kong Innovation and Technology Funding.
2019, Guanghua Scholarship.
2017, Outstanding Graduate of Xidian University.
2016, National Scholarship.
2015, National Inspirational Scholarship.

🔥 News

2026.01: 🎉🎉 Our paper “D2CIM: A 28nm 53.3 TFLOP/W Decoding Digital CIM Macro for Efficient FlashMLA-based LLM Inference” has been accepted for oral presentation at 2026 IEEE Custom Integrated Circuits Conference (CICC) , Apri 2026, Seattle, USA! Top IC Conference
2025.08: 🎉🎉 My paper as the main corresponding author “CDCC: A HIGH-EFFICIENCY SRAM-BASED CHARGE-DOMAIN COMPUTE-IN-MEMORY MACRO WITH COMPLEMENT COMPENSATION DESIGN FOR AI APPLICATIONS” has been accepted by the IEEE ASICON 2025 as Oral presentation paper, Aug 2025, Yunan, China! (Best Paper Award)
2025.06: 🎉🎉 My paper “YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-situ Multiply Arithmetic for Large-scale AI” has been accepted by 62nd ACM/IEEE Design Automation Conference (DAC), Jun 2025, San Francisco, USA! (CCF-A Conference, Acceptance Rate: 23%)
2025.06: 🎉🎉 One collaborative paper “SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy” has been accepted by 62nd ACM/IEEE Design Automation Conference (DAC), Jun 2025, San Francisco, USA! (CCF-A Conference, Acceptance Rate: 23%)
2024.06: 🎉🎉 My paper “AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multi-Bit Compute and Interconnect” has been accepted by 62nd ACM/IEEE Design Automation Conference (DAC) 2024 Work-in-Progress Poster Session!
2022.11: 🎉🎉 My paper “A Brain-inspired ADC-free SRAM-Based In-Memory Computing Macro with High-Precision MAC for AI Application” has been accepted by IEEE Transactions on Circuits and Systems II: Express Briefs (IEEE TCAS-II)! Spotlight Article
2022.06: 🎉🎉 My paper “High-efficiency data conversion interface for reconfigurable function-in-memory computing” has been accepted by IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI)! (CCF-B Journal)
2022.06: 🎉🎉 One paper as co-first author “Sub-femto-Joule energy consumption memory device based on van der Waals heterostructure for in-memory computing” has been accepted by Chip! (JCR Q1, IF = 7.1)
2021.10: 🎉🎉 My paper “HPSW-CIM: A Novel ReRAM-Based Computing-in-Memory Architecture with Constant-Term Circuit for Full Parallel Hybrid-Precision-Signed-Weight MAC Operation” has been accepted by IEEE International Symposium on Circuits and Systems (IEEE ISCAS) 2022!
2021.06： 🎉🎉 One paper as co-first author “One transistor one electrolyte‐gated transistor based spiking neural network for power‐efficient neuromorphic computing system” has been accepted by Advanced Functional Materials! (TOP Journal, IF=19.4)

📝 Main Publications

[D2CIM: A 28nm 53.3 TFLOP/W Decoding Digital CIM Macro for Efficient FlashMLA-based LLM Inference].
YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-situ Multiply Arithmetic for Large-Scale AI. Zihao Xuan, Yuxuan Yang, Wei Xuan, Zijia Su, Song Chen, Yi Kang. 2025, *62nd ACM/IEEE Design Automation Conference (DAC).
A Brain-inspired ADC-free SRAM-Based In-Memory Computing Macro with High-Precision MAC for AI Application. Zihao Xuan, Chang Liu, Yue Zhang, Yuan Li, Yi Kang. 2022, *IEEE Transactions on Circuits and Systems II: Express Briefs (IEEE TCAS-II).
High-efficiency data conversion interface for reconfigurable function-in-memory computing. Zihao Xuan, Yi Kang. 2022, *IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
HPSW-CIM: A Novel ReRAM-Based Computing-in-Memory Architecture with Constant-Term Circuit for Full Parallel Hybrid-Precision-Signed-Weight MAC Operation. Zihao Xuan, Yue Zhang, Yuan Li, Chang Liu, Yi Kang. 2022, *IEEE International Symposium on Circuits and Systems (ISCAS).
Sub-femto-Joule energy consumption memory device based on van der Waals heterostructure for in-memory computing. Zijia Su†, Zihao Xuan†, Jing Liu, Yi Kang, Chun-Sen Liu, Cheng-Jie Zuo. 2020, *Chip. (co-first author)
One transistor one electrolyte‐gated transistor based spiking neural network for power‐efficient neuromorphic computing system. Yue Li†, Zihao Xuan†, Jikai Lu, Zhongrui Wang, Xumeng Zhang, Zuheng Wu, Yongzhou Wang, Han Xu, Chunmeng Dou, Yi Kang, Qi Liu, Hangbing Lv, Dashan Shang. 2019, *Advanced Functional Materials. (co-first author)

📝 Collaborative Publications

[SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy]. Wei Xuan, Zhongrui Wang, Lang Feng, Ning Lin, Zihao Xuan, Rongliang Fu, Tsung-Yi Ho, Yuzhong Jiao and Luhong Liang. 2025, 62nd ACM/IEEE Design Automation Conference (DAC).
A dynamic decoder with speculative termination for low latency inference in spiking neural networks. Yuxuan Yang, Zihao Xuan, Song Chen, Yi Kang. 2025, *Neurocomputing.
HNM-CIM: An Algorithm-Hardware Co-designed SRAM-based CIM for Transformer Acceleration Exploiting Hybrid N: M Sparsity. Yuang Ma, Yulong Meng, Zihao Xuan, Song Chen, Yi Kang. 2025, *ACM Transactions on Design Automation of Electronic Systems.
A neuromorphic hardware architecture based on TTFS coding with temporal quantization for spiking neural networks. Yuxuan Yang, Qihu Xie, Zihao Xuan, Song Chen, Yi Kang. 2025, *Integration.
Broadband Artificial Tetrachromatic Synaptic Devices Composed of 2D/3D Integrated WSe2 -GaN-based Dual-Channel Floating Gate Transistors. Zijia Su, Yong Yan, Maorong Sun, Zihao Xuan, Hengxiao Cheng, Dongyang Luo, Zhixiang Gao, Huabin Yu, Haochen Zhang, Chengjie Zuo, and Haiding Sun. 2024, Advanced Functional Materials.
TQ-TTFS: High-Accuracy and Energy-Efficient Spiking Neural Networks Using Temporal Quantization Time-to-First-Spike Neuron. Yuxuan Yang, Zihao Xuan, Yi Kang. 2024 *29th Asia and South Pacific Design Automation Conference (ASP-DAC).
An 1.38 nJ/Inference Clock-Free Mixed-Signal Neuromorphic Architecture Using ReL-PSP Function and Computing-in-Memory. Wenbing Fang, Zihao Xuan, Song Chen, Yi Kang. 2023, *IEEE Biomedical Circuits and Systems Conference (BioCAS).
A 28nm 15.09 nJ/inference Neuromorphic Processor with SRAM-Based Charge Domain in-Memory-Computing. Yuchao Zhang, Zihao Xuan, Yi Kang. 2023, *IEEE 15th International Conference on ASIC (ASICON).
A 40-nm 202.3 nJ/classification neuromorphic architecture employing in-SRAM charge-domain compute. Chang Liu, Zihao Xuan, Yi Kang. 2021, *IEEE 14th International Conference on ASIC (ASICON).
One transistor one electrolyte-gated transistor for supervised learning in SNNs. Jikai Lu, Yue Li, Zihao Xuan, Han Xu, Shuyu Wu, Zhongrui Wang, Shibing Long, Qi Liu, Dashan Shang. 2021, *IEEE Electron Device Letters.
Vertical sandwich gate-all-around field-effect transistors with self-aligned high-k metal gates and small effective-gate-length variation. Xiaogen Yin, Yongkui Zhang, Huilong Zhu, GL Wang, JJ Li, AY Du, C Li, LH Zhao, WX Huang, H Yang, L Xie, XZ Ai, YB Zhang, KP Jia, ZH Wu, XL Ma, QZ Zhang, SJ Mao, JJ Xiang, JF Gao, XB He, GB Bai, YH Lu, N Zhou, ZZ Kong, Y Zhang, J Zhao, SS Ma, ZH Xuan, YY Li, L Li, QH Zhang, JH Han, RL Chen, Y Qu, T Yang, J Luo, JF Li, HX Yin, H Radamson, C Zhao, WW Wang, TC Ye. 2019, *IEEE Electron Device Letters.

🔍 Manuscript Reviews

IEEE TCAS-I 2022, 2025; AFM 2025; Sensors 2025. Advance Science 2025, TCAD 2025, TVLSI 2025.

💬 Invited Talks

More to come…

🌐 Internships